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? semiconductor components industries, llc, 2002 april, 2002 rev. 4 1 publication order number: nlast44599/d nlast44599 low voltage single supply dual dpdt analog switch the nlast44599 is an advanced cmos dualindependent dpdt (double poledouble throw) analog switch, fabricated with silicon gate cmos technology. it achieves highspeed propagation delays and low on resistances while maintaining cmos lowpower dissipation. this dpdt controls analog and digital voltages that may vary across the full powersupply range (from v cc to gnd). the device has been designed so the on resistance (r on ) is much lower and more linear over input voltage than r on of typical cmos analog switches. the channelselect input structure provides protection when voltages between 0 v and 5.5 v are applied, regardless of the supply voltage. this input structure helps prevent device destruction caused by supply voltage input/output voltage mismatch, battery backup, hot insertion, etc. the nlast44599 can also be used as a quad 2to1 multiplexer demultiplexer analog switch with two select pins that each controls two multiplexerdemultiplexers. ? select pins compatible with ttl levels ? channel select input overvoltage tolerant to 5.5 v ? fast switching and propagation speeds ? breakbeforemake circuitry ? low power dissipation: i cc = 2 a (max) at t a = 25 c ? diode protection provided on channel select input ? improved linearity and lower on resistance over input voltage ? latchup performance exceeds 300 ma ? esd performance: hbm > 2000 v; mm > 200 v ? chip complexity: 158 fets figure 1. marking diagrams see detailed ordering and shipping information in the package dimensions section on page 10 of this data sheet. ordering information 1 8 16 9 nlat 4459 alyw a = assembly location l = wafer lot y = year w = work week qfn16 mn suffix case 485g 1 16 tssop16 dt suffix case 948f 1 t alyw 16 1 16 http://onsemi.com
nlast44599 http://onsemi.com 2 v cc nc d1 com d no d0 select cd nc c 1 com c no c 0 nc b 1 gnd no b 0 com b nc a 1 com a no a 0 e lect ab 116 2 3 4 5 6 7 8 9 10 11 12 13 14 15 u u com a select ab x1 no a 0 u nc a 1 figure 1. logic diagram qfn16 package tssop16 package 1 2 3 7 4 5 6 8 9 10 11 12 13 14 15 16 com d u no b 0 u nc b 1 u no c 0 u nc c 1 u no d 0 u nc d 1 select cd x1 u com b u com c u com d 0/1 2/3 0/1 2/3 0 1 2 3 0 1 2 3 com a no a 0 v cc nc d 1 no d 0 scd nc c 1 nc a 1 sab no b 0 com b nc b1 gnd no c 0 com c figure 2. iec logic symbol see tssop16 switch configuration function table l h select xy nc to com no to com on channel l h select ab or cd nc to com no to com on channel
nlast44599 http://onsemi.com 3 maximum ratings symbol parameter value unit v cc positive dc supply voltage 0.5 to 7.0 v v is analog input voltage (v no or v com ) 0.5 v is v cc 0.5 v v in digital select input voltage 0.5 v i 7.0 v i ik dc current, into or out of any pin 50 ma p d power dissipation in still air tssop16 450 mw t stg storage temperature range 65 to 150 c t l lead temperature, 1 mm from case for 10 seconds 260 c t j junction temperature under bias 150 c msl moisture sensitivity level 1 f r flammability rating oxygen index: 30% 35% ul94vo (0.125 in) v esd esd withstand voltage human body model (note 1) machine model (note 2) charged device model (note 3) 2000 200 1000 v i latchup latchup performance above v cc and below gnd at 125 c (note 4) 300 ma ja thermal resistance tssop16 164 c/w absolute maximum continuous ratings are those values beyond which damage to the device may occur. extended exposure to these co nditions or conditions beyond those indicated may adversely affect device reliability. functional operation under absolutemaximumrated conditions is not implied. functional operation should be restricted to the recommended operating conditions. 1. tested to eia/jesd22a114a. 2. tested to eia/jesd22a115a. 3. tested to jesd22c101a. 4. tested to eia/jesd78. recommended operating conditions symbol parameter min max unit v cc dc supply voltage 2.0 5.5 v v in digital select input voltage gnd 5.5 v v is analog input voltage (nc, no, com) gnd v cc v t a operating temperature range 55 125 c t r , t f input rise or fall time, select v cc = 3.3 v 0.3 v v cc = 5.0 v 0.5 v 0 0 100 20 ns/v device junction temperature versus time to 0.1% bond failures junction temperature c time, hours time, y ears 80 1,032,200 117.8 90 419,300 47.9 100 178,700 20.4 110 79,600 9.4 120 37,000 4.2 130 17,800 2.0 140 8,900 1.0 1 1 10 100 1000 failure rate of plastic = ceramic until intermetallics occur figure 3. failure rate vs. time junction temperature normalized failure rate time, years t j = 130 c t j = 120 c t j = 110 c t j = 100 c t j = 90 c t j = 80 c
nlast44599 http://onsemi.com 4 dc characteristics digital section (voltages referenced to gnd) guaranteed limit symbol parameter condition v cc 55 c to 25 c 85 c 125 c unit v ih minimum highlevel input voltage, select inputs 3.0 4.5 5.5 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 v v il maximum lowlevel input voltage, select inputs 3.0 4.5 5.5 0.5 0.8 0.8 0.5 0.8 0.8 0.5 0.8 0.8 v i in maximum input leakage current, select inputs v in = 5.5 v or gnd 5.5 0.2 2.0 2.0 a i off power off leakage current v in = 5.5 v or gnd 0 10 10 10 a i cc maximum quiescent supply current select and v is = v cc or gnd 5.5 4.0 4.0 8.0 a dc electrical characteristics analog section guaranteed limit symbol parameter condition v cc 55 c to 25 c 85 c 125 c unit r on maximum aono resistance (figures 17 23) v in = v il or v ih v is = gnd to v cc i in i 10.0 ma 2.5 3.0 4.5 5.5 85 45 30 25 95 50 35 30 105 55 40 35 r flat (on) on resistance flatness (figures 17 23) v in = v il or v ih i in i 10.0 ma v is = 1 v, 2 v, 3.5 v 4.5 4 4 5 i nc(off) i no(off) no or nc off leakage current (figure 9) v in = v il or v ih v no or v nc = 1.0 v com 4.5 v 5.5 1 10 100 na i com(on) com on leakage current (figure 9) v in = v il or v ih v no 1.0 v or 4.5 v with v nc floating or v no 1.0 v or 4.5 v with v no floating v com = 1.0 v or 4.5 v 5.5 1 10 100 na
nlast44599 http://onsemi.com 5 ac electrical characteristics (input t r = t f = 3.0 ns) guaranteed maximum limit v cc v is 55 c to 25 c 85 c 125 c symbol parameter test conditions (v) (v) min typ* max min max min max unit t on turnon time (figures 12 and 13) r l = 300 c l = 35 pf (figures 5 and 6) 2.5 3.0 4.5 5.5 2.0 2.0 3.0 3.0 5 5 2 2 23 16 11 9 35 24 16 14 5 5 2 2 38 27 19 17 5 5 2 2 41 30 22 20 ns t off turnoff time (figures 12 and 13) r l = 300 c l = 35 pf (figures 5 and 6) 2.5 3.0 4.5 5.5 2.0 2.0 3.0 3.0 1 1 1 1 7 5 4 3 12 10 6 5 1 1 1 1 15 13 9 8 1 1 1 1 18 16 12 11 ns t bbm minimum breakbeforemake time v is = 3.0 v (figure 4) r l = 300 c l = 35 pf 2.5 3.0 4.5 5.5 2.0 2.0 3.0 3.0 1 1 1 1 12 11 6 5 1 1 1 1 1 1 1 1 ns *typical characteristics are at 25 c. typical @ 25, vcc = 5.0 v c in c no or c nc c com c (on) maximum input capacitance, select input analog i/o (switch off) common i/o (switch off) feedthrough (switch on) 8 10 10 20 pf additional application characteristics (voltages referenced to gnd unless noted) v cc typical symbol parameter condition v 25 c unit bw maximum onchannel 3 db bandwidth or minimum frequency response (figure 11) v in = 0 dbm v in centered between v cc and gnd (figure 7) 3.0 4.5 5.5 145 170 175 mhz v onl maximum feedthrough on loss v in = 0 dbm @ 100 khz to 50 mhz v in centered between v cc and gnd (figure 7) 3.0 4.5 5.5 3 3 3 db v iso offchannel isolation (figure 10) f = 100 khz; v is = 1 v rms v in centered between v cc and gnd (figure 7) 3.0 4.5 5.5 93 93 93 db q charge injection select input to common i/o (figure 15) v in = v cc to gnd, f is = 20 khz t r = t f = 3 ns r is = 0 , c l = 1000 pf q = c l * v out (figure 8) 3.0 5.5 1.5 3.0 pc thd total harmonic distortion thd noise (figure 14) f is = 20 hz to 100 khz, r l = rgen = 600 , c l = 50 pf v is = 5.0 v pp sine wave 5.5 0.1 % vct channel to channel crosstalk f = 100 khz; v is = 1 v rms v in centered between v cc and gnd (figure 7) 5.5 3.0 90 90 db
nlast44599 http://onsemi.com 6 figure 4. t bbm (time breakbeforemake) output dut 300 w 35 pf v cc switch select pin 90% output input v cc gnd 90% of v oh gnd figure 5. t on /t off 50% 50% 90% 90% t on t off v oh output input v cc 0 v figure 6. t on /t off dut open 35 pf v cc input 50% 50% 10% t on t off output input v cc 0 v 10% 300 w 0.1 f t bmm output v out v ol v out v oh v ol dut open v cc input output 300 w 35 pf v out 0.1 f
nlast44599 http://onsemi.com 7 channel switch control/s test socket is normalized. off isolation is measured across an off channel. on loss is the bandwidth of an on switch. v iso , bandwidth and v onl are independent of the input signal direction. v iso = off channel isolation = 20 log for v in at 100 khz v onl = on channel loss = 20 log for v in at 100 khz to 50 mhz bandwidth (bw) = the frequency 3 db below v onl v ct = use v iso setup and test to all other switch analog input/outputs terminated with 50 output dut input 50 w 50 w generator reference transmitted figure 7. off channel isolation/on channel loss (bw)/crosstalk (on channel to off channel)/v onl 50 w v out v in v out v in off on off d v out v cc gnd output v in c l dut figure 8. charge injection: (q) v in open output 55 20 leakage (na) figure 9. switch leakage vs. temperature 1 i no(off) temperature ( c) 0.01 25 0.001 0.1 70 85 125 i com(on) i com(off) v cc = 5.0 v 10 100
nlast44599 http://onsemi.com 8 figure 10. offchannel isolation figure 11. typical bandwidth and phase shift 1 0.1 0.01 3.0 30 2.5 4.5 35 figure 12. t on and t off vs. v cc at 25 c v cc (volts) figure 13. t on and t off vs. temp temperature ( c) time (ns) time (ns) figure 14. total harmonic distortion plus noise vs. frequency frequency (khz) figure 15. charge injection vs. com voltage v com (v) thd + noise (%) q (pc) 10 1 100 55 25 125 40 20 15 25 0 034 2 15 t on v cc = 3 v v cc = 5 v 2.5 2.0 1.5 1.0 0.5 0 0.5 v inpp = 5.0 v v cc = 5.5 v v inpp = 3.0 v v cc = 3.6 v 10 5 t off t on (ns) t off (ns) v cc = 4.5 v 3.5 4 30 20 15 25 0 10 5 85 0.01 10 1 0.1 (db) 100 0 off isolation frequency (mhz) 100 200 80 60 40 20 v cc = 5.0 v t a = 25 c 0.01 10 1 0.1 100 300 frequency (mhz) phase ( ) bandwidth (onresponse) phase shift v cc = 5.0 v t a = 25 c 5 15 35 10 20 30 25 0 +5 +10 +15 (db) 2.0 4.0 6.0 10.0 0 1.0 3.0 5.0 7.0 9.0 8.0
nlast44599 http://onsemi.com 9 0 5 10 15 20 25 30 35 40 45 50 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 25 c 55 c 85 c 125 c 85 c 55 c 125 c 0 10 20 30 40 50 60 70 80 90 100 0.0 0.5 1.0 1.5 2.0 2.5 25 c 55 c 85 c 25 c 125 c 0 10 20 30 40 50 60 70 80 90 100 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0.0 2.0 1.0 3.0 4.0 5.0 6.0 temperature ( c) figure 16. i cc vs. temp, v cc = 3 v and 5 v i cc (na) 80 100 60 40 20 0 figure 17. r on vs. v cc, temp = 25 c v is (vdc) figure 18. r on vs temp, v cc = 2.0 v r on ( w ) r on ( w ) figure 19. r on vs. temp, v cc = 2.5 v v is (vdc) figure 20. r on vs. temp, v cc = 3.0 v v is (vdc) r on ( w ) r on ( w ) 40 60 80 20 0 100 20 120 v cc = 2.0 v v cc = 2.5 v v cc = 3.0 v v cc = 4.0 v v cc = 5.5 v v cc = 3.0 v v cc = 5.0 v 10 1 0.1 100 0.01 0.001 0.0001 0.00001 figure 21. r on vs. temp, v cc = 4.5 v v is (vdc) 0 5 10 15 20 25 30 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 r on ( w ) v is (vdc) 25 c 55 c 125 c 85 c
nlast44599 http://onsemi.com 10 figure 22. r on vs. temp, v cc = 5.0 v figure 23. r on vs. temp, v cc = 5.5 v 20 15 r on ( w ) 10 25 v is (vdc) 5 0 0.0 2.0 1.5 1.0 0.5 2.5 3.0 3.5 4.0 4.5 5.0 25 c 85 c 125 c 55 c 20 15 r on ( w ) 10 25 v is (vdc) 5 0 0.0 2.0 1.5 1.0 0.5 2.5 3.0 3.5 4.0 4.5 5.0 5.5 25 c 85 c 125 c 55 c device ordering information device nomenclature device order number circuit indicator technology device function package suffix tape and reel suffix package type tape and reel size NLAST44599MNR2 nl as 44599 mn r2 qfn 7inch/2500 unit nlast44599dtr2 nl as 44599 dt r2 tssop 13inch/2500 unit nlast44599mn nl as 44599 mn qfn 124 unit rail nlast44599dt nl as 44599 dt tssop 96 unit rail figure 24. user direction of feed pin1/product orientation carrier tape
nlast44599 http://onsemi.com 11 package dimensions qfn16 mn suffix case 485g01 issue o x m 0.10 (0.004) t t x note 3 seating plane l a m y b n 0.25 (0.010) t 0.25 (0.010) t j c k r 0.08 (0.003) t g e h f p d y 1 4 58 12 9 16 13 dim min max min max inches millimeters a 3.00 bsc 0.118 bsc b 3.00 bsc 0.118 bsc c 0.80 1.00 0.031 0.039 d 0.23 0.28 0.009 0.011 g 0.50 bsc 0.020 bsc h 0.875 0.925 0.034 0.036 j 0.20 ref 0.008 ref k 0.00 0.05 0.000 0.002 l 0.35 0.45 0.014 0.018 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeters. 3. dimension d applies to plated terminal and is measured between 0.25 and 0.30 mm from terminal. 4. coplanarity applies to the exposed pad as well as the terminals. e 1.75 1.85 0.069 0.073 f 1.75 1.85 0.069 0.073 m 1.50 bsc 0.059 bsc n 1.50 bsc 0.059 bsc p 0.875 0.925 0.034 0.036 r 0.60 0.80 0.024 0.031
nlast44599 http://onsemi.com 12 package dimensions tssop16 dt suffix case 948f01 issue o ??? ??? dim min max min max inches millimeters a 4.90 5.10 0.193 0.200 b 4.30 4.50 0.169 0.177 c --- 1.20 --- 0.047 d 0.05 0.15 0.002 0.006 f 0.50 0.75 0.020 0.030 g 0.65 bsc 0.026 bsc h 0.18 0.28 0.007 0.011 j 0.09 0.20 0.004 0.008 j1 0.09 0.16 0.004 0.006 k 0.19 0.30 0.007 0.012 k1 0.19 0.25 0.007 0.010 l 6.40 bsc 0.252 bsc m 0 8 0 8 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash. protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. dimension k does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the k dimension at maximum material condition. 6. terminal numbers are shown for reference only. 7. dimension a and b are to be determined at datum plane -w-. section nn seating plane ident. pin 1 1 8 16 9 detail e j j1 b c d a k k1 h g ?? ?? detail e f m l 2x l/2 u s u 0.15 (0.006) t s u 0.15 (0.006) t s u m 0.10 (0.004) v s t 0.10 (0.004) t v w 0.25 (0.010) 16x ref k n n on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provid ed in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into t he body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indem nify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized u se, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employ er. publication ordering information japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. nlast44599/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 8002829855 toll free usa/canada

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